The present invention relates generally to delay circuits and, particularly, to delay circuits that provide a stable delay for a wide range of operating and process conditions.
A delay circuit generates an output signal characterized by selected signal transitions that are delayed from corresponding transitions of a pulsed input signal. Delay circuits are widely used in all types of electronic circuits, including integrated circuits such as digital memories. Ideally, a given delay circuit should provide a constant delay for a wide range of operating conditions. This is a challenge, as most delay circuits used in integrated circuits comprise transistors, logic gates and/or op amps, whose switching performance is highly dependent on the operating temperature and power supply voltage (VDD), which are likely to vary during operation. For example, the operating temperature can vary between xe2x88x9210 degrees Centigrade (xc2x0 C.) and 100xc2x0 C. and VDD for a 3.3 volt (V) integrated circuit can vary between 2.8 V and 3.8 V. Another factor affecting delay circuits is process variation. For example, a delay circuit performs differently depending on whether the fabrication process is fast or slow (i.e., produces fast or slow transistors) and on whether the p-channel and n-channel transistors have symmetrical or asymmetrical characteristics.
FIG. 1 is a schematic diagram of a prior art delay circuit 5 that can be implemented as part of an integrated circuit. Delay circuit 5 comprises eight (or any even number) inverters I1, I2, . . . , I8 connected in a chain. The delay between the input IN and the output OUT of the delay circuit 5 can be varied by changing the number of inverters in the chain or by adjusting the size (i.e., the channel width and length) of the transistors in the inverters.
Unfortunately, the delay produced by the delay circuit 5 is highly sensitive to variations in temperature, power supply voltage and process. The delay of the delay circuit 5 is largely determined by the current drive and logic threshold of the inverters I1 to I8 in the delay circuit. Since these inverter characteristics are highly dependent upon temperature, power supply voltage and process conditions, the delay of the delay circuit can vary significantly.
FIG. 2 is a schematic diagram of a second prior art delay circuit 10. Delay circuit 10 comprises a resistor R and a capacitor C arranged in an RC network configuration. The delay between the input IN and the output OUT of the delay circuit 10 is determined by the time constant R*C, where R is the resistance of the resistor R and C is the capacitance of the capacitor C. More specifically, if a 0 V to VDD step input signal is applied to the input IN, the output OUT reaches a voltage of 0.63*VDD in the time R*C. Therefore, the delay of the delay circuit 10 can be adjusted by varying the values of the resistor R and capacitor C appropriately.
Unlike the delay circuit 5 mentioned earlier, the delay circuit 10 provides a delay that is relatively stable despite changes in temperature, power supply voltage or process. This is because the delay is determined by the values of the resistor R and capacitor C, which are not highly sensitive to changes in temperature, power supply voltage or process.
However, the maximum delay that the delay circuit 10 can produce for an input pulse signal is limited. Specifically, the delay circuit 10 cannot produce a delay greater than the duration of the input pulse. If the time constant of the delay circuit 10 is set to produce a delay greater than the input pulse duration, the delay circuit will not transfer the input pulse to the output. Due to its relatively slow rise time, the output of the delay circuit will not have sufficient time to rise to the voltage representing a logical xe2x80x9c1xe2x80x9d before the end of the input pulse.
Therefore, there is a need for a delay circuit that provides a delay that is stable over a wide range of temperature, power supply voltage and process conditions. In addition, the delay circuit should be able to provide a delay that is not significantly limited in duration.
In summary, the present invention is a pulse delay circuit that provides a delay for a pulsed input signal that does not vary significantly under changing temperature, power supply voltage or process conditions. Furthermore, the delay provided by the pulse delay circuit is not significantly limited in duration.
The pulse delay circuit of the present invention comprises a pulse detector, an RC delay circuit coupled to the pulse detector and a pulsed signal generator coupled to the RC delay circuit. The pulse detector includes an input for receiving a pulsed signal and an output for generating a leveled signal that transitions between a first voltage and a second voltage (i.e., from the first voltage to the second voltage or vice versa) whenever the pulsed signal transitions from the first voltage to the second voltage. The RC delay circuit includes an input coupled to the output of the pulse detector and an output for generating a delayed leveled signal that transitions between the first voltage and the second voltage whenever the leveled signal transitions in the same direction, separated by a delay at least partially determined by an RC time constant associated with the RC delay circuit. The pulsed signal generator includes an input coupled to the output of the RC delay circuit and an output for generating a delayed pulsed signal containing a pulse of a predetermined width whenever the delayed leveled signal transitions in at least one direction between the first voltage and the second voltage. The delay of the pulse delay circuit is primarily determined by the RC time constant of the RC delay circuit.
In one embodiment of the present invention, the pulsed signal generator generates a pulse whenever the delayed leveled signal transitions from either the first voltage to the second voltage or the second voltage to the first voltage.
In an alternative embodiment of the present invention, the RC delay circuit further includes a second output for generating a second delayed leveled signal that transitions between the first voltage and the second voltage whenever the leveled signal transitions in the opposite direction, separated by a delay at least partially determined by a second RC time constant associated with the RC delay circuit. In addition, the pulsed signal generator further includes a second input coupled to the second output of the RC delay circuit, wherein the pulsed signal generator generates a pulse whenever either the first or second delayed leveled signal transitions from the first voltage to the second voltage.